1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent alignment thereto.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After gate areas have been defined on a semiconductor substrate and implant regions (e.g., source/drain regions) have been formed in the substrate, an interlevel dielectric is formed over the topography to make electrical contact to the gate areas and the implant regions. Interconnects are then formed across the interlevel dielectric to connect the implant regions and/or the gate areas through ohmic contacts formed earlier through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
A technique known as xe2x80x9cphotolithographyxe2x80x9d is generally used to pattern the various levels of an integrated circuit. Photolithography entails transferring an optical image to a photosensitive film from a patterned mask plate (i.e., reticle) placed in proximity to the film. The photosensitive film, i.e., xe2x80x9cphotoresistxe2x80x9d is formed upon the layer of material to be patterned. A mask plate having both opaque and transparent regions is placed above the resist. Radiation is transmitted through only the transparent portions of the mask plate to the resist. The solubility of resist regions exposed to the radiation is altered by a photochemical reaction. A solvent may be used to remove the resist areas of higher solubility. The resulting patterned resist film serves to protect underlying conductive or dielectric material from etching or ion implantation.
It is critical to align successive layers of an integrated circuit to each other to ensure proper operation of the circuit. In particular, the mask plate pattern must be properly aligned to previously formed features in a semiconductor topography during the lithography process. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other, and isolation of structures that should be coupled to each other. Typically, an alignment system, such as a stepper, is used to align the mask plate to the semiconductor topography. The alignment system may employ an alignment mark (e.g., a trench in the form of a geometric shape, such as a square, a xe2x80x9c+xe2x80x9d, or an xe2x80x9cXxe2x80x9d) which has been formed in the substrate as a reference point. Although the original alignment mark may be covered by subsequently deposited layers, the step height of the alignment mark (the depth of the trench) is replicated in those layers. The alignment system directs a laser beam to the replicated alignment mark residing in the most recently deposited layer. The light striking the replicated alignment mark is reflected back to sensing devices which detect the exact position of the alignment mark. Alignment is achieved by moving the mask plate until a feature, i.e., an alignment guide, in the mask plate is correctly positioned with respect to the alignment mark.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when an interconnect is placed across a dielectric layer having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. The presence of such elevational disparities therefore makes it difficult to print high resolution features.
Techniques involving chemical and mechanical abrasion (e.g., chemical-mechanical polishing) to planarize or remove the surface irregularities have grown in popularity. As shown in FIG. 1, a typical chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d) process involves placing a semiconductor wafer 4 face-down on a polishing pad 6 which lies on or is attached to a rotatable table or platen 8. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad 6 and semiconductor wafer 4 may be rotated while a carrier 2 holding wafer 4 applies a downward force F upon polishing pad 6. A xe2x80x9cslurryxe2x80x9d consisting of an abrasive and a fluid-based chemical is deposited from a conduit 9 positioned above pad 6 onto the surface of polishing pad 6. The slurry may fill the space between pad 6 and the surface of wafer 4. The polishing process may involve a chemical in the slurry reacting with the surface material being polished. The rotational movement of polishing pad 6 relative to wafer 4 causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer 4. The pad 6 itself may also physically remove some material from the surface of the wafer 4. The abrasive slurry particles are typically composed of silica, alumina, or ceria.
Unfortunately, planarizing the layers of an integrated circuit may also planarize the alignment mark areas which have been transferred to those layers from the substrate. Absent the topography of the alignment marks, the lithography alignment system may be incapable of properly aligning a mask plate to the previously patterned layers. The commonly used solution to dealing with planarized alignment marks uses a photolithographic step to expose the alignment mark areas and protect the rest of the substrate with resist. In the next step, the planarized dielectric in the alignment mark areas is etched away so as to recover the original pattern of the alignment marks. This solution therefore adds two steps to the process flow. It would therefore be desirable to develop methods for preserving alignment marks in a substrate and precisely aligning a mask plate to a planarized semiconductor topography having such marks. That is, an alignment technique is desired which does not require the replication of alignment marks from the substrate into subsequent layers to properly align those layers.
The problems outlined above are in large part solved by an embodiment of the present invention in which a substantially transparent dielectric is retained above one or more alignment marks while polishing the dielectric. The optical property of the alignment mark is preserved even though the polishing process removes its replicated pattern from the overlying dielectric. The alignment mark may be formed by etching an alignment mark trench into a semiconductor substrate. The semiconductor substrate may comprise a bulk semiconducting material, such as Si, SiGe, Ge, GaAs, SiGeAs, etc., which may be conventionally doped with N-dopants, such as P, As, Sb, S, Se, and/or P-dopants, such as B, BF2, upon which subsequent thin films are deposited and/or patterned. A silicon nitride (xe2x80x9cnitridexe2x80x9d) layer may be deposited on the substrate-embodied alignment mark during a shallow trench isolation process, before or after forming the shallow trench. The nitride layer may form a mask during the formation of densely packed isolation trenches within the substrate. Advantageously, because of its translucence, the nitride layer may be retained above the alignment mark (in the alignment mark trench) while a transparent dielectric is deposited across the topography. No time-consuming selective etch technique is therefore required to remove the nitride layer from the alignment mark prior to the deposition of the transparent dielectric. The transparent dielectric may advantageously fill both the alignment mark trench and the isolation trench (or trenches).
The isolation trenches are formed within the area of the substrate allotted for the ensuing integrated circuit while the alignment mark trench is formed outside this area of the substrate. The densely packed configuration of the isolation trenches may result in the non-planarity of the dielectric above those trenches. In particular, because of the proximity of the isolation trenches to each other as the transparent dielectric is deposited, closely spaced recessed regions tend to develop in the dielectric above the isolation trenches. In contrast, the alignment mark trench (or trenches) is relatively farther away from each other and/or from other structures whose changes affect the topography. The dielectric placed above the alignment mark trench includes a recessed region that is not as closely packed with other recessed regions. Further, the depth of the alignment mark trench may be less than that of the isolation trenches, resulting in the recessed region over the alignment mark trench being smaller in size than the recessed regions over the isolation trenches. A larger elevational disparity may therefore exist in a portion of the dielectric above the isolation trenches than in a portion of the dielectric above the alignment mark trench. The ratios of the width, length, and/or depth of the alignment mark trench to those respective dimensions of the isolation trench may vary according to design preferences and criteria. The following table shows possible ranges for the depths and widths of the alignment mark trench and the isolation trench, as well as the preferred depths and widths:
The upper surface of the transparent dielectric is polished by a technique which polishes non-planar surfaces faster than relatively planar surfaces. Because the dielectric above the alignment mark has less elevational disparity than the dielectric above the isolation trenches, it is generally planarized at a slower rate than the dielectric above the isolation trenches. Once the dielectric surface above the alignment mark is planarized, its polish rate becomes so slow that very little dielectric is further removed from above the alignment mark. However, the non-planar dielectric surface above the isolation trenches is polished at a relatively high rate for a longer period of time until it too becomes substantially planarized. Consequently, more of the dielectric may be removed from above the isolation trenches than from above the alignment mark trench during polishing. As such, the dielectric surface extending over the isolation trenches may be polished to a level commensurate with the upper surface of the nitride layer, while the dielectric surface extending over the alignment mark trench is only removed to a level spaced above the nitride layer, typically from 100 xc3x85 to 5,000 A above the nitride layer, preferably 200 xc3x85 xc3x85 to 3,000 xc3x85, and more preferably 300 xc3x85 to 2,500 xc3x85.
Although the alignment mark pattern is not transferred to the remaining transparent dielectric, a reticle may be accurately aligned to a polycrystalline silicon/nitride stack subsequently formed upon the transparent dielectric. That is, the alignment mark may be detected by passing light (e.g., laser light) through the transparent dielectric and the nitride layer to the alignment mark in the silicon substrate. The transparent dielectric may comprise a material that has a refractive index substantially dissimilar to the refractive index of the silicon substrate. Examples of such dielectrics include silicon dioxide (xe2x80x9coxidexe2x80x9d), alumina, alumina silicates, and oxynitrides of aluminum and/or silicon, which may be conventionally doped with phosphorous, and/or boron, fluoride, etc. Preferably, the dielectric is SiO2. As such, the presence of the transparent dielectric within the alignment mark trench provides for a high reflectivity of light (e.g., laser light) at the substrate surface within the trench. The nitride and transparent dielectric layers comprise a visually discernable thickness upon the trench dissimilar from a visually discernable thickness upon the substrate laterally adjacent the trench. Therefore, the reflectivity disparity between the trench area and the substrate outside the trench is sufficient to afford good detection of the alignment mark. Absent the transparent dielectric and the nitride layer, a polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) layer would be deposited into the trench upon the substrate surface. It is believed that a very low reflectivity of light would be observed at the polysilicon/Si interface since these materials have similar compositions and refractive indexes. Consequently, the alignment mark would not be visible to a detection device. Placing the planarized transparent dielectric and the nitride layer having a refractive index substantially dissimilar to that of Si within the alignment mark trench therefore provides for better detection of the alignment mark. This alignment scheme may avoid the case of additional steps to recover the original pattern (topography) of the alignment marks.
According to an embodiment, alignment marks are formed within areas of a semiconductor substrate not to be occupied by devices of an ensuing integrated circuit. For example, the alignment marks may be placed near the edges of a silicon wafer. Each alignment mark may be formed by etching an alignment mark trench into an upper portion of the substrate. Thereafter, a xe2x80x9cpadxe2x80x9d oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. The pad oxide layer serves to relieve the mechanical stresses that normally exist between silicon and nitride. Isolation trenches which may be deeper than the alignment mark trenches are subsequently formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A liner oxide layer may then be thermally grown upon the sidewalls and floor of the isolation trenches. A substantially transparent dielectric is then deposited across the semiconductor topography to a level spaced above the first nitride layer. In this manner, both the isolation trenches and the alignment mark trenches are filled.
The upper surface of the transparent dielectric may then be polished. Preferably, a xe2x80x9cfixed-abrasivexe2x80x9d technique is used to polish the dielectric. The fixed-abrasive technique involves placing a liquid which is substantially free of particulate matter between the dielectric surface and an abrasive polishing surface. The liquid contains no chemical constituent that would necessarily react with the topography. The polishing surface is moved relative to the semiconductor topography so as to polish the dielectric. The first nitride layer may serve as a polish stop, assuming that the polish rate of nitride is relatively slow. The liquid applied to the polishing surface preferably comprises deionized water, however, other liquids which have a near-neutral pH value may alternatively be directed onto the abrasive polishing surface. A more acidic or basic liquid might undesirably increase the removal rate of the first nitride layer. The pH that is chosen for the polishing process is one suitable for the dielectric surface and the abrasive polishing pad. The polishing surface comprises a polymer-based matrix embedded with particles selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide. The abrasive polishing surface belongs to a polishing pad which is substantially resistant to deformation even when placed across an elevationally recessed region of relatively large lateral dimension (e.g., over 200 microns lateral dimension). Therefore, the pad is non-conformal to the underlying surface and thus does not come in contact with elevationally recessed regions of the dielectric.
It is believed that the particles dispersed throughout the abrasive surface in combination with the polishing liquid interact chemically and physically with those regions of the dielectric placed in contact with the particles. However, the liquid alone is believed to have little effect on the dielectric and thus does not remove recessed areas of the dielectric which the abrasive surface does not contact. As such, elevationally raised regions of the dielectric are removed at a substantially faster rate than elevationally recessed regions. The polish rate slows down significantly upon areas of the dielectric that approach planarity. The transparent dielectric above the alignment marks is substantially planarized before it is completely removed from above the first nitride layer. The polish rate of the transparent dielectric above the alignment marks decreases at this point, allowing the dielectric to remain above the first nitride layer. In contrast, the transparent dielectric above the isolation trenches is removed from the first nitride layer, which is where the dielectric surface is substantially planarized.
In an alternate embodiment, the transparent dielectric may be polished using well-known CMP. That is, the frontside of the semiconductor topography may be forced against a CMP polishing pad while the polishing pad and the topography are rotated relative to each other. A CMP slurry entrained with abrasive particles, e.g., ceria, silica, or alumina, is dispensed upon the polishing pad surface to aid in the removal of the transparent dielectric. During the CMP process, the slurry may undesirably react with the dielectric in elevationally recessed regions, releasing the surface material from its union with the bulk of the dielectric. Further, the polishing pad, being somewhat conformal to the topological surface, may deform to the elevationally raised and recessed topography by xe2x80x9cbowingxe2x80x9d in an arcuate pattern in response to a force being applied thereto. The deformation of the polishing pad thusmay further contribute to the removal of the elevationally recessed regions by physically stripping the reacted surface material of the dielectric. Therefore, while the removal rate of elevationally raised regions of the dielectric may be greater than that of the elevationally recessed regions, a significant amount of the elevationally recessed regions may, unfortunately, undergo removal. This phenomena is known as the xe2x80x9cdishingxe2x80x9d effect and may reduce the degree of planarization that can be achieved by the CMP process. The elevational disparities in the dielectric surface spaced above the alignment mark and the isolation trenches thus might be impossible to eliminate completely. Using the slurry-based CMP process, however, still leaves a significant thickness of the dielectric over the alignment mark to provide for detection of the alignment mark even after the dielectric over the substrate adjacent the isolation trenches has been removed.
Subsequent to polishing the dielectric, portions of the first nitride layer and the pad oxide layer which are no longer covered by the transparent dielectric are etched from the substrate surface. In this manner, the substrate surface proximate the trench isolation structures is exposed while the substrate surface proximate the alignment marks remains concealed. A gate dielectric is then formed upon those exposed portions of the substrate surface. A polysilicon layer and a second nitride layer are sequentially deposited across the topography. Photoresist is then spin-on deposited across the second nitride layer. An alignment system, e.g., a stepper, is used to align a reticle to the semiconductor topography. The alignment system first passes light, e.g., laser light, through the materials overlying the alignment marks to the alignment mark areas. The reflectivity of light at the alignment mark surfaces is in contrast to the reflectivity of light at the substrate surfaces outside the alignment mark areas. This contrast allows the alignment marks to be detected. Using the alignment marks as references, the alignment mark system then positions the reticle above the photoresist. The photoresist is patterned by passing radiation, e.g., ultraviolet light, through transparent regions of the reticle to the photoresist. Select portions of the second nitride layer and the polysilicon layer not covered by the photoresist are then etched. In this manner, polysilicon gate conductors are aligned to regions of the substrate laterally spaced from the trench isolation structures. A capping nitride layer residing upon the gate conductors electrically isolates the gate conductor from subsequently formed contacts and interconnects.